Verilog and VHDL support for Code Block Macro


We have a requirement to add Verilog and VHDL support for code block macro. Could you please let us know if it's possible?

I have tried to add the support using the information provided in the following URL.

However it's not working. It's throwing an error "Can't find brush for: Verilog".

Please let us know details regarding this.


1 answer

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Hi Ajith

I tested this just now on my Confluence 6.5.0 instance, and it does appear to be working. Can you let me know what version of Confluence you're running?

It appears to have been a bug in the past, but was fixed after 5.9.14 and 5.10.3:

Kind regards,




We are using the version 5.9.11. 

You tested using this ==> ? 

Or any other methods? please let me know. 




Hi Ajith,

Since this was the known bug, I recommend upgrading to 5.10.3 or higher and it will resolve your issue.

Let us know if you have any trouble.

Kind regards,

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