Verilog is one of the widely used language for hardware design. Currently, Code Block Macro doesn't support verilog for syntax highliting. Is there any plan for support this lanugages?
I think many companies uses verilog or VHDL for hardware design. And there are a lot of syntax hightling code for thouse languages. I think the job to support these languages is a quite simple for developers of code block macro.
다행이 답이 있습니다!
You're in luck, because there is a solution. The Code Block macro uses syntaxhighlighter brushes in the background, and these can be installed manually (if you are using the server version).
Here is a brush for Verilog:
and here is a brush for VHDL:
Save those files to your computer, then go to the General Settings (you must be Confluence Admin)
Are you using the Cloud version of Confluence? In that case, it's even easier. Just install the free Better Code for Confluence add-on, and that has VHDL and Verilog syntax highlighting built-in.
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